{"id":1257,"date":"2023-03-16T12:07:42","date_gmt":"2023-03-16T12:07:42","guid":{"rendered":"https:\/\/262235.xyz\/?p=1257"},"modified":"2023-03-16T12:07:42","modified_gmt":"2023-03-16T12:07:42","slug":"1257","status":"publish","type":"post","link":"https:\/\/lyvba.com\/index.php\/2023\/03\/16\/1257\/","title":{"rendered":"RARS \u6c47\u7f16\u6a21\u62df\u5668\u652f\u6301\u7684RISC-V\u6307\u4ee4"},"content":{"rendered":"

Supported Instructions (\u652f\u6301\u7684\u6307\u4ee4)<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Example Usage<\/th>\n\u4e2d\u6587\u63cf\u8ff0<\/th>\nDescription<\/th>\n<\/tr>\n<\/thead>\n
add t1,t2,t3<\/td>\n\u52a0\u6cd5\uff1a\u8bbe t1 \u4e3a\uff08t2 \u52a0 t3\uff09<\/td>\nAddition: set t1 to (t2 plus t3)<\/td>\n<\/tr>\n
addi t1,t2,-100<\/td>\n\u52a0\u6cd5\u7acb\u5373\u6570\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\uff08t2 \u52a0\u4e0a\u5e26\u7b26\u53f7\u7684 12 \u4f4d\u7acb\u5373\u6570\uff09<\/td>\nAddition immediate: set t1 to (t2 plus signed 12-bit immediate)<\/td>\n<\/tr>\n
and t1,t2,t3<\/td>\n\u6309\u4f4d\u4e0e\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a t2 \u548c t3 \u7684\u6309\u4f4d\u4e0e<\/td>\nBitwise AND : Set t1 to bitwise AND of t2 and t3<\/td>\n<\/tr>\n
andi t1,t2,-100<\/td>\n\u6309\u4f4d\u4e0e\u7acb\u5373\u6570\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a t2 \u7684\u6309\u4f4d\u4e0e\u548c\u7b26\u53f7\u6269\u5c55\u7684 12 \u4f4d\u7acb\u5373\u6570<\/td>\nBitwise AND immediate : Set t1 to bitwise AND of t2 and sign-extended 12-bit immediate<\/td>\n<\/tr>\n
auipc t1,10000<\/td>\n\u5c06\u9ad8\u4f4d\u7acb\u5373\u6570\u6dfb\u52a0\u5230 pc\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\uff08pc \u52a0\u4e0a\u9ad8\u4f4d 20 \u4f4d\u7acb\u5373\u6570\uff09<\/td>\nAdd upper immediate to pc: set t1 to (pc plus an upper 20-bit immediate)<\/td>\n<\/tr>\n
beq t1,t2,label<\/td>\nBranch if equal : \u5982\u679c t1 \u548c t2 \u76f8\u7b49\u5219\u5206\u652f\u5230\u6807\u7b7e\u5730\u5740\u5904\u7684\u8bed\u53e5<\/td>\nBranch if equal : Branch to statement at label's address if t1 and t2 are equal<\/td>\n<\/tr>\n
bge t1,t2,label<\/td>\nBranch if greater than or equal\uff1a\u5982\u679c t1 \u5927\u4e8e\u6216\u7b49\u4e8e t2\uff0c\u5219\u5206\u652f\u5230\u6807\u7b7e\u5730\u5740\u5904\u7684\u8bed\u53e5<\/td>\nBranch if greater than or equal: Branch to statement at label's address if t1 is greater than or equal to t2<\/td>\n<\/tr>\n
bgeu t1,t2,label<\/td>\nBranch if greater than or equal to (unsigned)\uff1a\u5982\u679c t1 \u5927\u4e8e\u6216\u7b49\u4e8e t2\uff0c\u5219\u5206\u652f\u5230\u6807\u7b7e\u5730\u5740\u5904\u7684\u8bed\u53e5\uff08\u65e0\u7b26\u53f7\u89e3\u91ca\uff09<\/td>\nBranch if greater than or equal to (unsigned): Branch to statement at label's address if t1 is greater than or equal to t2 (with an unsigned interpretation)<\/td>\n<\/tr>\n
blt t1,t2,label<\/td>\nBranch if less than\uff1a\u5982\u679c t1 \u5c0f\u4e8e t2\uff0c\u5219\u5206\u652f\u5230\u6807\u7b7e\u5730\u5740\u5904\u7684\u8bed\u53e5<\/td>\nBranch if less than: Branch to statement at label's address if t1 is less than t2<\/td>\n<\/tr>\n
bltu t1,t2,label<\/td>\nBranch if less than (unsigned)\uff1a\u5982\u679c t1 \u5c0f\u4e8e t2\uff0c\u5219\u5206\u652f\u5230\u6807\u7b7e\u5730\u5740\u5904\u7684\u8bed\u53e5\uff08\u65e0\u7b26\u53f7\u89e3\u91ca\uff09<\/td>\nBranch if less than (unsigned): Branch to statement at label's address if t1 is less than t2 (with an unsigned interpretation)<\/td>\n<\/tr>\n
bne t1,t2,label<\/td>\nBranch if not equal : \u5982\u679c t1 \u548c t2 \u4e0d\u76f8\u7b49\u5219\u5206\u652f\u5230\u6807\u7b7e\u5730\u5740\u5904\u7684\u8bed\u53e5<\/td>\nBranch if not equal : Branch to statement at label's address if t1 and t2 are not equal<\/td>\n<\/tr>\n
csrrc t0, fcsr, t1<\/td>\n\u539f\u5b50\u8bfb\u53d6\/\u6e05\u9664 CSR\uff1a\u4ece CSR \u8bfb\u53d6\u5230 t0 \u5e76\u6839\u636e t1 \u6e05\u9664 CSR \u7684\u4f4d<\/td>\nAtomic Read\/Clear CSR: read from the CSR into t0 and clear bits of the CSR according to t1<\/td>\n<\/tr>\n
csrrci t0, fcsr, 10<\/td>\n\u7acb\u5373\u539f\u5b50\u8bfb\u53d6\/\u6e05\u9664 CSR\uff1a\u4ece CSR \u8bfb\u53d6\u5230 t0 \u5e76\u6839\u636e\u5e38\u91cf\u6e05\u9664 CSR \u7684\u4f4d<\/td>\nAtomic Read\/Clear CSR Immediate: read from the CSR into t0 and clear bits of the CSR according to a constant<\/td>\n<\/tr>\n
csrrs t0, fcsr, t1<\/td>\n\u539f\u5b50\u8bfb\u53d6\/\u8bbe\u7f6e CSR\uff1a\u4ece CSR \u8bfb\u53d6\u5230 t0 \u5e76\u5c06\u903b\u8f91\u6216 t1 \u8bfb\u53d6\u5230 CSR<\/td>\nAtomic Read\/Set CSR: read from the CSR into t0 and logical or t1 into the CSR<\/td>\n<\/tr>\n
csrrsi t0, fcsr, 10<\/td>\n\u7acb\u5373\u539f\u5b50\u8bfb\u53d6\/\u8bbe\u7f6e CSR\uff1a\u4ece CSR \u8bfb\u53d6\u5230 t0 \u5e76\u5c06\u903b\u8f91\u6216\u5e38\u91cf\u8bfb\u53d6\u5230 CSR<\/td>\nAtomic Read\/Set CSR Immediate: read from the CSR into t0 and logical or a constant into the CSR<\/td>\n<\/tr>\n
csrrw t0, fcsr, t1<\/td>\n\u539f\u5b50\u8bfb\/\u5199 CSR\uff1a\u4ece CSR \u8bfb\u5165 t0 \u5e76\u5c06 t1 \u5199\u5165 CSR<\/td>\nAtomic Read\/Write CSR: read from the CSR into t0 and write t1 into the CSR<\/td>\n<\/tr>\n
csrrwi t0, fcsr, 10<\/td>\n\u539f\u5b50\u8bfb\/\u5199 CSR \u7acb\u5373\uff1a\u4ece CSR \u8bfb\u53d6\u5230 t0 \u5e76\u5c06\u5e38\u91cf\u5199\u5165 CSR<\/td>\nAtomic Read\/Write CSR Immediate: read from the CSR into t0 and write a constant into the CSR<\/td>\n<\/tr>\n
div t1,t2,t3<\/td>\n\u9664\u6cd5\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a t2\/t3 \u7684\u7ed3\u679c<\/td>\nDivision: set t1 to the result of t2\/t3<\/td>\n<\/tr>\n
divu t1,t2,t3<\/td>\n\u9664\u6cd5\uff1a\u4f7f\u7528\u65e0\u7b26\u53f7\u9664\u6cd5\u5c06 t1 \u8bbe\u7f6e\u4e3a t2\/t3 \u7684\u7ed3\u679c<\/td>\nDivision: set t1 to the result of t2\/t3 using unsigned division<\/td>\n<\/tr>\n
ebreak<\/td>\n\u6682\u505c\u6267\u884c<\/td>\nPause execution<\/td>\n<\/tr>\n
ecall<\/td>\n\u53d1\u51fa\u7cfb\u7edf\u8c03\u7528\uff1a\u6267\u884ca7\u4e2d\u503c\u6307\u5b9a\u7684\u7cfb\u7edf\u8c03\u7528<\/td>\nIssue a system call : Execute the system call specified by value in a7<\/td>\n<\/tr>\n
fadd.d f1, f2, f3, dyn<\/td>\n\u6d6e\u52a8 ADD\uff0864 \u4f4d\uff09\uff1a\u5c06 f1 \u5206\u914d\u7ed9 f2 + f3<\/td>\nFloating ADD (64 bit): assigns f1 to f2 + f3<\/td>\n<\/tr>\n
fadd.s f1, f2, f3, dyn<\/td>\n\u6d6e\u52a8 ADD\uff1a\u5c06 f1 \u5206\u914d\u7ed9 f2 + f3<\/td>\nFloating ADD: assigns f1 to f2 + f3<\/td>\n<\/tr>\n
fclass.d t1, f1<\/td>\n\u5bf9\u4e00\u4e2a\u6d6e\u70b9\u6570\uff0864\u4f4d\uff09\u8fdb\u884c\u5206\u7c7b<\/td>\nClassify a floating point number (64 bit)<\/td>\n<\/tr>\n
fclass.s t1, f1<\/td>\n\u5bf9\u4e00\u4e2a\u6d6e\u70b9\u6570\u8fdb\u884c\u5206\u7c7b<\/td>\nClassify a floating point number<\/td>\n<\/tr>\n
fcvt.d.s t1, f1, dyn<\/td>\n\u5c06 float \u8f6c\u6362\u4e3a double\uff1a\u5c06 f2 \u7684\u503c\u5206\u914d\u7ed9 f1<\/td>\nConvert a float to a double: Assigned the value of f2 to f1<\/td>\n<\/tr>\n
fcvt.d.w f1, t1, dyn<\/td>\n\u4ece\u6574\u6570\u8f6c\u6362\u4e3a\u53cc\u7cbe\u5ea6\uff1a\u5c06 t1 \u7684\u503c\u8d4b\u7ed9 f1<\/td>\nConvert double from integer: Assigns the value of t1 to f1<\/td>\n<\/tr>\n
fcvt.d.wu f1, t1, dyn<\/td>\n\u4ece\u65e0\u7b26\u53f7\u6574\u6570\u8f6c\u6362\u53cc\u7cbe\u5ea6\u6570\uff1a\u5c06 t1 \u7684\u503c\u8d4b\u7ed9 f1<\/td>\nConvert double from unsigned integer: Assigns the value of t1 to f1<\/td>\n<\/tr>\n
fcvt.s.d t1, f1, dyn<\/td>\n\u5c06\u53cc\u7cbe\u5ea6\u578b\u8f6c\u6362\u4e3a\u6d6e\u70b9\u578b\uff1a\u5c06 f2 \u7684\u503c\u5206\u914d\u7ed9 f1<\/td>\nConvert a double to a float: Assigned the value of f2 to f1<\/td>\n<\/tr>\n
fcvt.s.w f1, t1, dyn<\/td>\n\u4ece\u6574\u6570\u8f6c\u6362\u4e3a\u6d6e\u70b9\u6570\uff1a\u5c06 t1 \u7684\u503c\u8d4b\u7ed9 f1<\/td>\nConvert float from integer: Assigns the value of t1 to f1<\/td>\n<\/tr>\n
fcvt.s.wu f1, t1, dyn<\/td>\n\u4ece\u65e0\u7b26\u53f7\u6574\u6570\u8f6c\u6362\u6d6e\u70b9\u6570\uff1a\u5c06 t1 \u7684\u503c\u8d4b\u7ed9 f1<\/td>\nConvert float from unsigned integer: Assigns the value of t1 to f1<\/td>\n<\/tr>\n
fcvt.w.d t1, f1, dyn<\/td>\n\u4ece\u53cc\u7cbe\u5ea6\u8f6c\u6362\u6574\u6570\uff1a\u5c06 f1 \u7684\u503c\uff08\u56db\u820d\u4e94\u5165\uff09\u5206\u914d\u7ed9 t1<\/td>\nConvert integer from double: Assigns the value of f1 (rounded) to t1<\/td>\n<\/tr>\n
fcvt.w.s t1, f1, dyn<\/td>\n\u4ece\u6d6e\u70b9\u6570\u8f6c\u6362\u6574\u6570\uff1a\u5c06 f1 \u7684\u503c\uff08\u56db\u820d\u4e94\u5165\uff09\u8d4b\u503c\u7ed9 t1<\/td>\nConvert integer from float: Assigns the value of f1 (rounded) to t1<\/td>\n<\/tr>\n
fcvt.wu.d t1, f1, dyn<\/td>\n\u4ece double \u8f6c\u6362\u672a\u7b7e\u540d\u7684\u6574\u6570\uff1a\u5c06 f1 \u7684\u503c\uff08\u56db\u820d\u4e94\u5165\uff09\u5206\u914d\u7ed9 t1<\/td>\nConvert unsinged integer from double: Assigns the value of f1 (rounded) to t1<\/td>\n<\/tr>\n
fcvt.wu.s t1, f1, dyn<\/td>\n\u5c06\u6d6e\u70b9\u6570\u8f6c\u6362\u4e3a\u65e0\u7b26\u53f7\u6574\u6570\uff1a\u5c06 f1 \u7684\u503c\uff08\u56db\u820d\u4e94\u5165\uff09\u8d4b\u503c\u7ed9 t1<\/td>\nConvert unsinged integer from float: Assigns the value of f1 (rounded) to t1<\/td>\n<\/tr>\n
fdiv.d f1, f2, f3, dyn<\/td>\n\u6d6e\u52a8 DIVide\uff0864 \u4f4d\uff09\uff1a\u5c06 f1 \u5206\u914d\u7ed9 f2 \/ f3<\/td>\nFloating DIVide (64 bit): assigns f1 to f2 \/ f3<\/td>\n<\/tr>\n
fdiv.s f1, f2, f3, dyn<\/td>\n\u6d6e\u52a8 DIVide\uff1a\u5c06 f1 \u5206\u914d\u7ed9 f2 \/ f3<\/td>\nFloating DIVide: assigns f1 to f2 \/ f3<\/td>\n<\/tr>\n
fence 1, 1<\/td>\n\u786e\u4fdd\u56f4\u680f\u4e4b\u524d\u7684 IO \u548c\u5185\u5b58\u8bbf\u95ee\u53d1\u751f\u5728\u4e0d\u540c\u7ebf\u7a0b\u67e5\u770b\u7684\u4ee5\u4e0b IO \u548c\u5185\u5b58\u8bbf\u95ee\u4e4b\u524d<\/td>\nEnsure that IO and memory accesses before the fence happen before the following IO and memory accesses as viewed by a different thread<\/td>\n<\/tr>\n
fence.i<\/td>\n\u786e\u4fdd\u6307\u4ee4\u5b58\u50a8\u5668\u7684\u5b58\u50a8\u5bf9\u6307\u4ee4\u63d0\u53d6\u53ef\u89c1<\/td>\nEnsure that stores to instruction memory are visible to instruction fetches<\/td>\n<\/tr>\n
feq.d t1, f1, f2<\/td>\nFloating EQuals\uff0864 \u4f4d\uff09\uff1a\u5982\u679c f1 = f2\uff0c\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 1\uff0c\u5426\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 0<\/td>\nFloating EQuals (64 bit): if f1 = f2, set t1 to 1, else set t1 to 0<\/td>\n<\/tr>\n
feq.s t1, f1, f2<\/td>\n\u6d6e\u52a8\u76f8\u7b49\uff1a\u5982\u679c f1 = f2\uff0c\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 1\uff0c\u5426\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 0<\/td>\nFloating EQuals: if f1 = f2, set t1 to 1, else set t1 to 0<\/td>\n<\/tr>\n
fld f1, -100(t1)<\/td>\n\u4ece\u5185\u5b58\u4e2d\u52a0\u8f7d\u4e00\u4e2a double<\/td>\nLoad a double from memory<\/td>\n<\/tr>\n
fle.d t1, f1, f2<\/td>\n\u5c0f\u4e8e\u6216\u7b49\u4e8e\u6d6e\u52a8\uff0864 \u4f4d\uff09\uff1a\u5982\u679c f1 <
\n;= f2\uff0c\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 1\uff0c\u5426\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 0<\/td>\n		Floating Less than or Equals (64 bit): if f1 <= f2, set t1 to 1, else set t1 to 0<\/td>\n<\/tr>\n
fle.s t1, f1, f2<\/td>\n\u6d6e\u52a8\u5c0f\u4e8e\u6216\u7b49\u4e8e\uff1a\u5982\u679c f1 <= f2\uff0c\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 1\uff0c\u5426\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 0<\/td>\nFloating Less than or Equals: if f1 <= f2, set t1 to 1, else set t1 to 0<\/td>\n<\/tr>\n
flt.d t1, f1, f2<\/td>\n\u5c0f\u4e8e\u6d6e\u52a8\uff0864 \u4f4d\uff09\uff1a\u5982\u679c f1 < f2\uff0c\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 1\uff0c\u5426\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 0<\/td>\nFloating Less Than (64 bit): if f1 < f2, set t1 to 1, else set t1 to 0<\/td>\n<\/tr>\n
flt.s t1, f1, f2<\/td>\n\u6d6e\u52a8\u5c0f\u4e8e\uff1a\u5982\u679c f1 < f2\uff0c\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 1\uff0c\u5426\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 0<\/td>\nFloating Less Than: if f1 < f2, set t1 to 1, else set t1 to 0<\/td>\n<\/tr>\n
flw f1, -100(t1)<\/td>\n\u4ece\u5185\u5b58\u4e2d\u52a0\u8f7d\u4e00\u4e2a\u6d6e\u70b9\u6570<\/td>\nLoad a float from memory<\/td>\n<\/tr>\n
fmadd.d f1, f2, f3, f4, dyn<\/td>\n\u878d\u5408\u4e58\u52a0\uff0864 \u4f4d\uff09\uff1a\u5c06 f2*f3+f4 \u5206\u914d\u7ed9 f1<\/td>\nFused Multiply Add (64 bit): Assigns f2*f3+f4 to f1<\/td>\n<\/tr>\n
fmadd.s f1, f2, f3, f4, dyn<\/td>\n\u878d\u5408\u4e58\u52a0\uff1a\u5c06 f2*f3+f4 \u5206\u914d\u7ed9 f1<\/td>\nFused Multiply Add: Assigns f2*f3+f4 to f1<\/td>\n<\/tr>\n
fmax.d f1, f2, f3<\/td>\nFloating MAXimum\uff0864 \u4f4d\uff09\uff1a\u5c06 f1 \u5206\u914d\u7ed9 f1 \u548c f3 \u4e2d\u7684\u8f83\u5927\u8005<\/td>\nFloating MAXimum (64 bit): assigns f1 to the larger of f1 and f3<\/td>\n<\/tr>\n
fmax.s f1, f2, f3<\/td>\nFloating MAXimum\uff1a\u5c06 f1 \u5206\u914d\u7ed9 f1 \u548c f3 \u4e2d\u7684\u8f83\u5927\u8005<\/td>\nFloating MAXimum: assigns f1 to the larger of f1 and f3<\/td>\n<\/tr>\n
fmin.d f1, f2, f3<\/td>\nFloating MINimum\uff0864 \u4f4d\uff09\uff1a\u5c06 f1 \u5206\u914d\u7ed9 f1 \u548c f3 \u4e2d\u7684\u8f83\u5c0f\u8005<\/td>\nFloating MINimum (64 bit): assigns f1 to the smaller of f1 and f3<\/td>\n<\/tr>\n
fmin.s f1, f2, f3<\/td>\nFloating MINimum\uff1a\u5c06 f1 \u5206\u914d\u7ed9 f1 \u548c f3 \u4e2d\u8f83\u5c0f\u7684\u4e00\u4e2a<\/td>\nFloating MINimum: assigns f1 to the smaller of f1 and f3<\/td>\n<\/tr>\n
fmsub.d f1, f2, f3, f4, dyn<\/td>\n\u878d\u5408\u4e58\u5b50\uff1a\u5c06 f2*f3-f4 \u5206\u914d\u7ed9 f1<\/td>\nFused Multiply Subatract: Assigns f2*f3-f4 to f1<\/td>\n<\/tr>\n
fmsub.s f1, f2, f3, f4, dyn<\/td>\n\u878d\u5408\u4e58\u5b50\uff1a\u5c06 f2*f3-f4 \u5206\u914d\u7ed9 f1<\/td>\nFused Multiply Subatract: Assigns f2*f3-f4 to f1<\/td>\n<\/tr>\n
fmul.d f1, f2, f3, dyn<\/td>\nFloating MULtiply\uff0864 \u4f4d\uff09\uff1a\u5c06 f1 \u5206\u914d\u7ed9 f2 * f3<\/td>\nFloating MULtiply (64 bit): assigns f1 to f2 * f3<\/td>\n<\/tr>\n
fmul.s f1, f2, f3, dyn<\/td>\nFloating MULtiply\uff1a\u5c06 f1 \u5206\u914d\u7ed9 f2 * f3<\/td>\nFloating MULtiply: assigns f1 to f2 * f3<\/td>\n<\/tr>\n
fmv.s.x f1, t1<\/td>\n\u79fb\u52a8\u6d6e\u70b9\u6570\uff1a\u4ece\u6574\u6570\u5bc4\u5b58\u5668\u4e2d\u79fb\u52a8\u8868\u793a\u6d6e\u70b9\u6570\u7684\u4f4d<\/td>\nMove float: move bits representing a float from an integer register<\/td>\n<\/tr>\n
fmv.x.s t1, f1<\/td>\n\u79fb\u52a8\u6d6e\u70b9\u6570\uff1a\u5c06\u8868\u793a\u6d6e\u70b9\u6570\u7684\u4f4d\u79fb\u52a8\u5230\u6574\u6570\u5bc4\u5b58\u5668<\/td>\nMove float: move bits representing a float to an integer register<\/td>\n<\/tr>\n
fnmadd.d f1, f2, f3, f4, dyn<\/td>\nFused Negate Multiply Add\uff0864 \u4f4d\uff09\uff1a\u5c06 -(f2*f3+f4) \u5206\u914d\u7ed9 f1<\/td>\nFused Negate Multiply Add (64 bit): Assigns -(f2*f3+f4) to f1<\/td>\n<\/tr>\n
fnmadd.s f1, f2, f3, f4, dyn<\/td>\nFused Negate Multiply Add\uff1a\u5c06 -(f2*f3+f4) \u5206\u914d\u7ed9 f1<\/td>\nFused Negate Multiply Add: Assigns -(f2*f3+f4) to f1<\/td>\n<\/tr>\n
fnmsub.d f1, f2, f3, f4, dyn<\/td>\n\u878d\u5408\u53d6\u53cd\u4e58\u6cd5\u51cf\u6cd5\uff1a\u5c06 -(f2*f3-f4) \u8d4b\u503c\u7ed9 f1<\/td>\nFused Negated Multiply Subatract: Assigns -(f2*f3-f4) to f1<\/td>\n<\/tr>\n
fnmsub.s f1, f2, f3, f4, dyn<\/td>\n\u878d\u5408\u53d6\u53cd\u4e58\u6cd5\u51cf\u6cd5\uff1a\u5c06 -(f2*f3-f4) \u8d4b\u503c\u7ed9 f1<\/td>\nFused Negated Multiply Subatract: Assigns -(f2*f3-f4) to f1<\/td>\n<\/tr>\n
fsd f1, -100(t1)<\/td>\n\u5c06\u53cc\u7cbe\u5ea6\u5b58\u50a8\u5230\u5185\u5b58<\/td>\nStore a double to memory<\/td>\n<\/tr>\n
fsgnj.d f1, f2, f3<\/td>\n\u6d6e\u70b9\u7b26\u53f7\u6ce8\u5165\uff0864\u4f4d\uff09\uff1a\u5c06f2\u7684\u7b26\u53f7\u4f4d\u66ff\u6362\u4e3af3\u7684\u7b26\u53f7\u4f4d\u8d4b\u503c\u7ed9f1<\/td>\nFloating point sign injection (64 bit): replace the sign bit of f2 with the sign bit of f3 and assign it to f1<\/td>\n<\/tr>\n
fsgnj.s f1, f2, f3<\/td>\n\u6d6e\u70b9\u7b26\u53f7\u6ce8\u5165\uff1a\u5c06f2\u7684\u7b26\u53f7\u4f4d\u66ff\u6362\u4e3af3\u7684\u7b26\u53f7\u4f4d\u8d4b\u503c\u7ed9f1<\/td>\nFloating point sign injection: replace the sign bit of f2 with the sign bit of f3 and assign it to f1<\/td>\n<\/tr>\n
fsgnjn.d f1, f2, f3<\/td>\n\u6d6e\u70b9\u7b26\u53f7\u6ce8\u5165\uff08\u53cd\u8f6c64\u4f4d\uff09\uff1a\u5c06f2\u7684\u7b26\u53f7\u4f4d\u66ff\u6362\u4e3af3\u7684\u76f8\u53cd\u7b26\u53f7\u4f4d\u8d4b\u503c\u7ed9f1<\/td>\nFloating point sign injection (inverted 64 bit): replace the sign bit of f2 with the opposite of sign bit of f3 and assign it to f1<\/td>\n<\/tr>\n
fsgnjn.s f1, f2, f3<\/td>\n\u6d6e\u70b9\u7b26\u53f7\u6ce8\u5165\uff08\u5012\u7f6e\uff09\uff1a\u5c06f2\u7684\u7b26\u53f7\u4f4d\u66ff\u6362\u4e3af3\u7684\u76f8\u53cd\u7b26\u53f7\u4f4d\u8d4b\u503c\u7ed9f1<\/td>\nFloating point sign injection (inverted): replace the sign bit of f2 with the opposite of sign bit of f3 and assign it to f1<\/td>\n<\/tr>\n
fsgnjx.d f1, f2, f3<\/td>\n\u6d6e\u70b9\u7b26\u53f7\u6ce8\u5165\uff08xor 64 bit\uff09\uff1a\u5c06f2\u7684\u7b26\u53f7\u4f4d\u4e0ef3\u7684\u7b26\u53f7\u4f4d\u5f02\u6216\u8d4b\u503c\u7ed9f1<\/td>\nFloating point sign injection (xor 64 bit): xor the sign bit of f2 with the sign bit of f3 and assign it to f1<\/td>\n<\/tr>\n
fsgnjx.s f1, f2, f3<\/td>\n\u6d6e\u70b9\u7b26\u53f7\u6ce8\u5165\uff08xor\uff09\uff1a\u5c06f2\u7684\u7b26\u53f7\u4f4d\u4e0ef3\u7684\u7b26\u53f7\u4f4d\u5f02\u6216\u8d4b\u503c\u7ed9f1<\/td>\nFloating point sign injection (xor): xor the sign bit of f2 with the sign bit of f3 and assign it to f1<\/td>\n<\/tr>\n
fsqrt.d f1, f2, dyn<\/td>\n\u6d6e\u52a8\u5e73\u65b9\u6839\uff0864 \u4f4d\uff09\uff1a\u5c06 f1 \u5206\u914d\u7ed9 f2 \u7684\u5e73\u65b9\u6839<\/td>\nFloating SQuare RooT (64 bit): Assigns f1 to the square root of f2<\/td>\n<\/tr>\n
fsqrt.s f1, f2, dyn<\/td>\n\u6d6e\u52a8\u5e73\u65b9\u6839\uff1a\u5c06 f1 \u5206\u914d\u7ed9 f2 \u7684\u5e73\u65b9\u6839<\/td>\nFloating SQuare RooT: Assigns f1 to the square root of f2<\/td>\n<\/tr>\n
fsub.d f1, f2, f3, dyn<\/td>\n\u6d6e\u52a8\u51cf\u6cd5\uff0864 \u4f4d\uff09\uff1a\u5c06 f1 \u5206\u914d\u7ed9 f2 - f3<\/td>\nFloating SUBtract (64 bit): assigns f1 to f2 - f3<\/td>\n<\/tr>\n
fsub.s f1, f2, f3, dyn<\/td>\n\u6d6e\u52a8\u51cf\u6cd5\uff1a\u5c06 f1 \u5206\u914d\u7ed9 f2 - f3<\/td>\nFloating SUBtract: assigns f1 to f2 - f3<\/td>\n<\/tr>\n
fsw f1, -100(t1)<\/td>\n\u5c06\u6d6e\u70b9\u6570\u5b58\u50a8\u5230\u5185\u5b58\u4e2d<\/td>\nStore a float to memory<\/td>\n<\/tr>\n
jal t1, target<\/td>\n\u8df3\u8f6c\u548c\u94fe\u63a5\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\u7a0b\u5e8f\u8ba1\u6570\u5668\uff08\u8fd4\u56de\u5730\u5740\uff09\uff0c\u7136\u540e\u8df3\u8f6c\u5230\u76ee\u6807\u5730\u5740\u5904\u7684\u8bed\u53e5<\/td>\nJump and link : Set t1 to Program Counter (return address) then jump to statement at target address<\/td>\n<\/tr>\n
jalr t1, t2, -100<\/td>\n\u8df3\u8f6c\u548c\u94fe\u63a5\u5bc4\u5b58\u5668\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\u7a0b\u5e8f\u8ba1\u6570\u5668\uff08\u8fd4\u56de\u5730\u5740\uff09\uff0c\u7136\u540e\u8df3\u8f6c\u5230 t2 + \u7acb\u5373\u6570\u5904\u7684\u8bed\u53e5<\/td>\nJump and link register: Set t1 to Program Counter (return address) then jump to statement at t2 + immediate<\/td>\n<\/tr>\n
lb t1, -100(t2)<\/td>\n\u5c06 t1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u5b57\u8282\u5730\u5740\u7684\u7b26\u53f7\u6269\u5c55 8 \u4f4d\u503c<\/td>\nSet t1 to sign-extended 8-bit value from effective memory byte address<\/td>\n<\/tr>\n
lbu t1, -100(t2)<\/td>\n\u5c06 t1 \u8bbe\u7f6e\u4e3a\u4ece\u6709\u6548\u5185\u5b58\u5b57\u8282\u5730\u5740\u5f00\u59cb\u7684\u96f6\u6269\u5c55 8 \u4f4d\u503c<\/td>\nSet t1 to zero-extended 8-bit value from effective memory byte address<\/td>\n<\/tr>\n
lh t1, -100(t2)<\/td>\n\u5c06 t1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u534a\u5b57\u5730\u5740\u7684\u7b26\u53f7\u6269\u5c55 16 \u4f4d\u503c<\/td>\nSet t1 to sign-extended 16-bit value from effective memory halfword address<\/td>\n<\/tr>\n
lhu t1, -100(t2)<\/td>\n\u5c06 t1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u534a\u5b57\u5730\u5740\u7684\u96f6\u6269\u5c55 16 \u4f4d\u503c<\/td>\nSet t1 to zero-extended 16-bit value from effective memory halfword address<\/td>\n<\/tr>\n
lui t1,10000<\/td>\n\u52a0\u8f7d\u9ad8\u7acb\u5373\u6570\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a 20 \u4f4d\u540e\u8ddf 12 \u4e2a 0<\/td>\nLoad upper immediate: set t1 to 20-bit followed by 12 0s<\/td>\n<\/tr>\n
lw t1, -100(t2)<\/td>\n\u5c06 t1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u5b57\u5730\u5740\u7684\u5185\u5bb9<\/td>\nSet t1 to contents of effective memory word address<\/td>\n<\/tr>\n
mul t1,t2,t3<\/td>\n\u4e58\u6cd5\uff1a\u5c06t1\u8bbe\u4e3at2*t3\u7684\u4f4e32\u4f4d<\/td>\nMultiplication: set t1 to the lower 32 bits of t2*t3<\/td>\n<\/tr>\n
mulh t1,t2,t3<\/td>\n\u4e58\u6cd5\uff1a\u4f7f\u7528\u6709\u7b26\u53f7\u4e58\u6cd5\u5c06 t1 \u8bbe\u7f6e\u4e3a t2*t3 \u7684\u9ad8 32 \u4f4d<\/td>\nMultiplication: set t1 to the upper 32 bits of t2*t3 using signed multiplication<\/td>\n<\/tr>\n
mulhsu t1,t2,t3<\/td>\n\u4e58\u6cd5\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a t2*t3 \u7684\u9ad8 32 \u4f4d\uff0c\u5176\u4e2d t2 \u662f\u6709\u7b26\u53f7\u7684\uff0ct3 \u662f\u65e0\u7b26\u53f7\u7684<\/td>\nMultiplication: set t1 to the upper 32 bits of t2*t3 where t2 is signed and t3 is unsigned<\/td>\n<\/tr>\n
mulhu t1,t2,t
\n3<\/td>\n		\u4e58\u6cd5\uff1a\u4f7f\u7528\u65e0\u7b26\u53f7\u4e58\u6cd5\u5c06 t1 \u8bbe\u7f6e\u4e3a t2*t3 \u7684\u9ad8 32 \u4f4d<\/td>\nMultiplication: set t1 to the upper 32 bits of t2*t3 using unsigned multiplication<\/td>\n<\/tr>\n
or t1,t2,t3<\/td>\n\u6309\u4f4d\u6216\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a t2 \u548c t3 \u7684\u6309\u4f4d\u6216<\/td>\nBitwise OR : Set t1 to bitwise OR of t2 and t3<\/td>\n<\/tr>\n
ori t1,t2,-100<\/td>\n\u6309\u4f4d\u6216\u7acb\u5373\u6570\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a t2 \u548c\u7b26\u53f7\u6269\u5c55\u7684 12 \u4f4d\u7acb\u5373\u6570\u7684\u6309\u4f4d\u6216<\/td>\nBitwise OR immediate : Set t1 to bitwise OR of t2 and sign-extended 12-bit immediate<\/td>\n<\/tr>\n
rem t1,t2,t3<\/td>\n\u4f59\u6570\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a t2\/t3 \u7684\u4f59\u6570<\/td>\nRemainder: set t1 to the remainder of t2\/t3<\/td>\n<\/tr>\n
remu t1,t2,t3<\/td>\n\u4f59\u6570\uff1a\u4f7f\u7528\u65e0\u7b26\u53f7\u9664\u6cd5\u5c06 t1 \u8bbe\u7f6e\u4e3a t2\/t3 \u7684\u4f59\u6570<\/td>\nRemainder: set t1 to the remainder of t2\/t3 using unsigned division<\/td>\n<\/tr>\n
sb t1, -100(t2)<\/td>\nStore byte : \u5c06t1\u7684\u4f4e8\u4f4d\u5b58\u5165\u6709\u6548\u5185\u5b58\u5b57\u8282\u5730\u5740<\/td>\nStore byte : Store the low-order 8 bits of t1 into the effective memory byte address<\/td>\n<\/tr>\n
sh t1, -100(t2)<\/td>\nStore halfword : \u5c06t1\u7684\u4f4e16\u4f4d\u5b58\u5165\u6709\u6548\u5185\u5b58\u534a\u5b57\u5730\u5740<\/td>\nStore halfword : Store the low-order 16 bits of t1 into the effective memory halfword address<\/td>\n<\/tr>\n
sll t1,t2,t3<\/td>\n\u5de6\u79fb\u903b\u8f91\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\u5c06 t2 \u5de6\u79fb t3 \u7684\u4f4e 5 \u4f4d\u4e2d\u7684\u503c\u6307\u5b9a\u7684\u4f4d\u6570\u7684\u7ed3\u679c<\/td>\nShift left logical: Set t1 to result of shifting t2 left by number of bits specified by value in low-order 5 bits of t3<\/td>\n<\/tr>\n
slli t1,t2,10<\/td>\n\u5de6\u79fb\u903b\u8f91\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\u5c06 t2 \u5de6\u79fb immediate \u6307\u5b9a\u7684\u4f4d\u6570\u7684\u7ed3\u679c<\/td>\nShift left logical : Set t1 to result of shifting t2 left by number of bits specified by immediate<\/td>\n<\/tr>\n
slt t1,t2,t3<\/td>\n\u8bbe\u7f6e\u5c0f\u4e8e\uff1a\u5982\u679c t2 \u5c0f\u4e8e t3\uff0c\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 1\uff0c\u5426\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 0<\/td>\nSet less than : If t2 is less than t3, then set t1 to 1 else set t1 to 0<\/td>\n<\/tr>\n
slti t1,t2,-100<\/td>\n\u8bbe\u7f6e\u5c0f\u4e8e\u7acb\u5373\u6570\uff1a\u5982\u679c t2 \u5c0f\u4e8e\u7b26\u53f7\u6269\u5c55\u7684 12 \u4f4d\u7acb\u5373\u6570\uff0c\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 1\uff0c\u5426\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 0<\/td>\nSet less than immediate : If t2 is less than sign-extended 12-bit immediate, then set t1 to 1 else set t1 to 0<\/td>\n<\/tr>\n
sltiu t1,t2,-100<\/td>\n\u8bbe\u7f6e\u5c0f\u4e8e\u65e0\u7b26\u53f7\u7acb\u5373\u6570\uff1a\u5982\u679c t2 \u5c0f\u4e8e\u4f7f\u7528\u65e0\u7b26\u53f7\u6bd4\u8f83\u8fdb\u884c\u7b26\u53f7\u6269\u5c55\u7684 16 \u4f4d\u7acb\u5373\u6570\uff0c\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 1\uff0c\u5426\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 0<\/td>\nSet less than immediate unsigned : If t2 is less than sign-extended 16-bit immediate using unsigned comparison, then set t1 to 1 else set t1 to 0<\/td>\n<\/tr>\n
sltu t1,t2,t3<\/td>\n\u8bbe\u7f6e\u5c0f\u4e8e\uff1a\u5982\u679c\u4f7f\u7528\u65e0\u7b26\u53f7\u6bd4\u8f83 t2 \u5c0f\u4e8e t3\uff0c\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 1\uff0c\u5426\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 0<\/td>\nSet less than : If t2 is less than t3 using unsigned comparision, then set t1 to 1 else set t1 to 0<\/td>\n<\/tr>\n
sra t1,t2,t3<\/td>\n\u53f3\u79fb\u7b97\u6cd5\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\u5c06 t2 \u7b26\u53f7\u6269\u5c55\u53f3\u79fb\u7684\u7ed3\u679c\uff0c\u5176\u4f4d\u6570\u7531 t3 \u7684\u4f4e 5 \u4f4d\u4e2d\u7684\u503c\u6307\u5b9a<\/td>\nShift right arithmetic: Set t1 to result of sign-extended shifting t2 right by number of bits specified by value in low-order 5 bits of t3<\/td>\n<\/tr>\n
srai t1,t2,10<\/td>\n\u53f3\u79fb\u7b97\u672f\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\u5c06 t2 \u7b26\u53f7\u6269\u5c55\u53f3\u79fb\u7acb\u5373\u6570\u6307\u5b9a\u7684\u4f4d\u6570\u7684\u7ed3\u679c<\/td>\nShift right arithmetic : Set t1 to result of sign-extended shifting t2 right by number of bits specified by immediate<\/td>\n<\/tr>\n
srl t1,t2,t3<\/td>\n\u53f3\u79fb\u903b\u8f91\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\u5c06 t2 \u53f3\u79fb t3 \u7684\u4f4e 5 \u4f4d\u4e2d\u7684\u503c\u6307\u5b9a\u7684\u4f4d\u6570\u7684\u7ed3\u679c<\/td>\nShift right logical: Set t1 to result of shifting t2 right by number of bits specified by value in low-order 5 bits of t3<\/td>\n<\/tr>\n
srli t1,t2,10<\/td>\n\u53f3\u79fb\u903b\u8f91\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\u5c06 t2 \u53f3\u79fb immediate \u6307\u5b9a\u7684\u4f4d\u6570\u7684\u7ed3\u679c<\/td>\nShift right logical : Set t1 to result of shifting t2 right by number of bits specified by immediate<\/td>\n<\/tr>\n
sub t1,t2,t3<\/td>\n\u51cf\u6cd5\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\uff08t2 \u51cf\u53bb t3\uff09<\/td>\nSubtraction: set t1 to (t2 minus t3)<\/td>\n<\/tr>\n
sw t1, -100(t2)<\/td>\nStore word\uff1a\u5c06t1\u7684\u5185\u5bb9\u5b58\u5165\u6709\u6548\u5185\u5b58\u5b57\u5730\u5740<\/td>\nStore word : Store contents of t1 into effective memory word address<\/td>\n<\/tr>\n
uret<\/td>\n\u4ece\u5904\u7406\u4e2d\u65ad\u6216\u5f02\u5e38\u8fd4\u56de\uff08\u5230 uepc\uff09<\/td>\nReturn from handling an interrupt or exception (to uepc)<\/td>\n<\/tr>\n
wfi<\/td>\n\u7b49\u5f85\u4e2d\u65ad<\/td>\nWait for Interrupt<\/td>\n<\/tr>\n
xor t1,t2,t3<\/td>\n\u6309\u4f4d\u5f02\u6216\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a t2 \u548c t3 \u7684\u6309\u4f4d\u5f02\u6216<\/td>\nBitwise XOR : Set t1 to bitwise XOR of t2 and t3<\/td>\n<\/tr>\n
xori t1,t2,-100<\/td>\n\u6309\u4f4d\u5f02\u6216\u7acb\u5373\u6570\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a t2 \u548c\u7b26\u53f7\u6269\u5c55\u7684 12 \u4f4d\u7acb\u5373\u6570\u7684\u6309\u4f4d\u5f02\u6216<\/td>\nBitwise XOR immediate : Set t1 to bitwise XOR of t2 and sign-extended 12-bit immediate<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Supported psuedo-instructions (\u652f\u6301\u7684\u4f2a\u6307\u4ee4)<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Example Usage<\/th>\n\u4e2d\u6587\u63cf\u8ff0<\/th>\nDescription<\/th>\n<\/tr>\n<\/thead>\n
addi t1,t2,%lo(label)<\/td>\nLoad Lower Address : \u8bbe\u7f6e t1 \u5230 t2 + \u4f4e 12 \u4f4d\u6807\u7b7e\u5730\u5740<\/td>\nLoad Lower Address : Set t1 to t2 + lower 12-bit label's address<\/td>\n<\/tr>\n
b label<\/td>\nBranch : \u65e0\u6761\u4ef6\u5206\u652f\u5230\u6807\u7b7e\u5904\u7684\u8bed\u53e5<\/td>\nBranch : Branch to statement at label unconditionally<\/td>\n<\/tr>\n
beqz t1,label<\/td>\nBranch if EQual Zero \uff1a\u5982\u679c t1 == 0 \u5219\u5206\u652f\u5230\u6807\u7b7e\u5904\u7684\u8bed\u53e5<\/td>\nBranch if EQual Zero : Branch to statement at label if t1 == 0<\/td>\n<\/tr>\n
bgez t1,label<\/td>\nBranch if Greater than or Equal to Zero \uff1a\u5982\u679c t1 >= 0\uff0c\u5219\u5206\u652f\u5230\u6807\u7b7e\u5904\u7684\u8bed\u53e5<\/td>\nBranch if Greater than or Equal to Zero : Branch to statement at label if t1 >= 0<\/td>\n<\/tr>\n
bgt t1,t2,label<\/td>\nBranch if Greater Than \uff1a\u5982\u679c t1 > t2 \u5219\u5206\u652f\u5230\u6807\u7b7e\u5904\u7684\u8bed\u53e5<\/td>\nBranch if Greater Than : Branch to statement at label if t1 > t2<\/td>\n<\/tr>\n
bgtu t1,t2,label<\/td>\nBranch if Greater Than Unsigned\uff1a\u5982\u679c t1 > t2\uff08\u65e0\u7b26\u53f7\u6bd4\u8f83\uff09\u5219\u5206\u652f\u5230\u6807\u7b7e\u5904\u7684\u8bed\u53e5<\/td>\nBranch if Greater Than Unsigned: Branch to statement at label if t1 > t2 (unsigned compare)<\/td>\n<\/tr>\n
bgtz t1,label<\/td>\nBranch if Greater Than\uff1a\u5982\u679c t1 > 0\uff0c\u5219\u5206\u652f\u5230\u6807\u7b7e\u5904\u7684\u8bed\u53e5<\/td>\nBranch if Greater Than: Branch to statement at label if t1 > 0<\/td>\n<\/tr>\n
ble t1,t2,label<\/td>\nBranch if Less or Equal \uff1a\u5982\u679c t1 <= t2 \u5219\u5206\u652f\u5230\u6807\u7b7e\u5904\u7684\u8bed\u53e5<\/td>\nBranch if Less or Equal : Branch to statement at label if t1 <= t2<\/td>\n<\/tr>\n
bleu t1,t2,label<\/td>\nBranch if Less or Equal Unsigned\uff1a\u5982\u679c t1 <= t2\uff08\u65e0\u7b26\u53f7\u6bd4\u8f83\uff09\uff0c\u5219\u5206\u652f\u5230\u6807\u7b7e\u5904\u7684\u8bed\u53e5<\/td>\nBranch if Less or Equal Unsigned : Branch to statement at label if t1 <= t2 (unsigned compare)<\/td>\n<\/tr>\n
blez t1,label<\/td>\nBranch if Less than or Equal to Zero\uff1a\u5982\u679c t1 <= 0\uff0c\u5219\u5206\u652f\u5230\u6807\u7b7e\u5904\u7684\u8bed\u53e5<\/td>\nBranch if Less than or Equal to Zero : Branch to statement at label if t1 <= 0<\/td>\n<\/tr>\n
bltz t1,label<\/td>\n\u5982\u679c\u5c0f\u4e8e\u96f6\u5219\u5206\u652f\uff1a\u5982\u679c t1 < 0\uff0c\u5219\u5206\u652f\u5230\u6807\u7b7e\u5904\u7684\u8bed\u53e5<\/td>\nBranch if Less Than Zero : Branch to statement at label if t1 < 0<\/td>\n<\/tr>\n
bnez t1,label<\/td>\nBranch if Not Equal Zero\uff1a\u5982\u679c t1 != 0\uff0c\u5219\u5206\u652f\u5230\u6807\u7b7e\u5904\u7684\u8bed\u53e5<\/td>\nBranch if Not Equal Zero : Branch to statement at label if t1 != 0<\/td>\n<\/tr>\n
call label<\/td>\nCALL\uff1a\u8c03\u7528\u8fdc\u5904\u7684\u5b50\u7a0b\u5e8f<\/td>\nCALL: call a far-away subroutine<\/td>\n<\/tr>\n
csrc t1, fcsr<\/td>\n\u6e05\u9664\u63a7\u5236\u548c\u72b6\u6001\u5bc4\u5b58\u5668\u4e2d\u7684\u4f4d<\/td>\nClear bits in control and status register<\/td>\n<\/tr>\n
csrci fcsr, 100<\/td>\n\u6e05\u9664\u63a7\u5236\u548c\u72b6\u6001\u5bc4\u5b58\u5668\u4e2d\u7684\u4f4d<\/td>\nClear bits in control and status register<\/td>\n<\/tr>\n
csrr t1, fcsr<\/td>\n\u8bfb\u53d6\u63a7\u5236\u548c\u72b6\u6001\u5bc4\u5b58\u5668<\/td>\nRead control and status register<\/td>\n<\/tr>\n
csrs t1, fcsr<\/td>\n\u8bbe\u7f6e\u63a7\u5236\u548c\u72b6\u6001\u5bc4\u5b58\u5668\u4e2d\u7684\u4f4d<\/td>\nSet bits in control and status register<\/td>\n<\/tr>\n
csrsi fcsr, 100<\/td>\n\u8bbe\u7f6e\u63a7\u5236\u548c\u72b6\u6001\u5bc4\u5b58\u5668\u4e2d\u7684\u4f4d<\/td>\nSet bits in control and status register<\/td>\n<\/tr>\n
csrw t1, fcsr<\/td>\n\u5199\u63a7\u5236\u548c\u72b6\u6001\u5bc4\u5b58\u5668<\/td>\nWrite control and status register\n<\/td>\n<\/tr>\n
csrwi fcsr, 100<\/td>\n\u5199\u63a7\u5236\u548c\u72b6\u6001\u5bc4\u5b58\u5668<\/td>\nWrite control and status register<\/td>\n<\/tr>\n
fabs.d f1, f2<\/td>\n\u5c06 f1 \u8bbe\u7f6e\u4e3a f2 \u7684\u7edd\u5bf9\u503c\uff0864 \u4f4d\uff09<\/td>\nSet f1 to the absolute value of f2 (64 bit)<\/td>\n<\/tr>\n
fabs.s f1, f2<\/td>\n\u5c06 f1 \u8bbe\u7f6e\u4e3a f2 \u7684\u7edd\u5bf9\u503c<\/td>\nSet f1 to the absolute value of f2<\/td>\n<\/tr>\n
fadd.d f1, f2, f3<\/td>\n\u6d6e\u52a8 ADD\uff0864 \u4f4d\uff09\uff1a\u5c06 f1 \u5206\u914d\u7ed9 f2 + f3<\/td>\nFloating ADD (64 bit): assigns f1 to f2 + f3<\/td>\n<\/tr>\n
fadd.s f1, f2, f3<\/td>\n\u6d6e\u52a8 ADD\uff1a\u5c06 f1 \u5206\u914d\u7ed9 f2 + f3<\/td>\nFloating ADD: assigns f1 to f2 + f3<\/td>\n<\/tr>\n
fcvt.d.s f1, f2<\/td>\n\u5c06float\u8f6c\u4e3adouble\uff1a\u5c06f2\u7684\u503c\u8d4b\u503c\u7ed9f1<\/td>\nConvert float to double: Assigned the value of f2 to f1<\/td>\n<\/tr>\n
fcvt.d.w f1, t1<\/td>\n\u4ece\u6709\u7b26\u53f7\u6574\u6570\u8f6c\u6362\u53cc\u7cbe\u5ea6\u6570\uff1a\u5c06 t1 \u7684\u503c\u8d4b\u7ed9 f1<\/td>\nConvert double from signed integer: Assigns the value of t1 to f1<\/td>\n<\/tr>\n
fcvt.d.wu f1, t1<\/td>\n\u4ece\u65e0\u7b26\u53f7\u6574\u6570\u8f6c\u6362\u53cc\u7cbe\u5ea6\u6570\uff1a\u5c06 t1 \u7684\u503c\u8d4b\u7ed9 f1<\/td>\nConvert double from unsigned integer: Assigns the value of t1 to f1<\/td>\n<\/tr>\n
fcvt.s.d f1, f2<\/td>\ndouble\u8f6cfloat\uff1a\u5c06f2\u7684\u503c\u8d4b\u503c\u7ed9f1<\/td>\nConvert double to float: Assigned the value of f2 to f1<\/td>\n<\/tr>\n
fcvt.s.w f1, t1<\/td>\n\u4ece\u6709\u7b26\u53f7\u6574\u6570\u8f6c\u6362\u6d6e\u70b9\u6570\uff1a\u5c06 t1 \u7684\u503c\u8d4b\u7ed9 f1<\/td>\nConvert float from signed integer: Assigns the value of t1 to f1<\/td>\n<\/tr>\n
fcvt.s.wu f1, t1<\/td>\n\u4ece\u65e0\u7b26\u53f7\u6574\u6570\u8f6c\u6362\u6d6e\u70b9\u6570\uff1a\u5c06 t1 \u7684\u503c\u8d4b\u7ed9 f1<\/td>\nConvert float from unsigned integer: Assigns the value of t1 to f1<\/td>\n<\/tr>\n
fcvt.w.d t1, f1<\/td>\n\u4ece\u53cc\u7cbe\u5ea6\u8f6c\u6362\u6709\u7b26\u53f7\u6574\u6570\uff1a\u5c06 f1 \u7684\u503c\uff08\u56db\u820d\u4e94\u5165\uff09\u5206\u914d\u7ed9 t1<\/td>\nConvert signed integer from double: Assigns the value of f1 (rounded) to t1<\/td>\n<\/tr>\n
fcvt.w.s t1, f1<\/td>\n\u4ece\u6d6e\u70b9\u6570\u8f6c\u6362\u6709\u7b26\u53f7\u6574\u6570\uff1a\u5c06 f1 \u7684\u503c\uff08\u56db\u820d\u4e94\u5165\uff09\u8d4b\u503c\u7ed9 t1<\/td>\nConvert signed integer from float: Assigns the value of f1 (rounded) to t1<\/td>\n<\/tr>\n
fcvt.wu.d t1, f1<\/td>\n\u4ece\u53cc\u7cbe\u5ea6\u8f6c\u6362\u65e0\u7b26\u53f7\u6574\u6570\uff1a\u5c06 f1 \u7684\u503c\uff08\u56db\u820d\u4e94\u5165\uff09\u5206\u914d\u7ed9 t1<\/td>\nConvert unsigned integer from double: Assigns the value of f1 (rounded) to t1<\/td>\n<\/tr>\n
fcvt.wu.s t1, f1<\/td>\n\u4ece\u6d6e\u70b9\u6570\u8f6c\u6362\u65e0\u7b26\u53f7\u6574\u6570\uff1a\u5c06 f1 \u7684\u503c\uff08\u56db\u820d\u4e94\u5165\uff09\u8d4b\u503c\u7ed9 t1<\/td>\nConvert unsigned integer from float: Assigns the value of f1 (rounded) to t1<\/td>\n<\/tr>\n
fdiv.d f1, f2, f3<\/td>\n\u6d6e\u52a8 DIVide\uff0864 \u4f4d\uff09\uff1a\u5c06 f1 \u5206\u914d\u7ed9 f2 \/ f3<\/td>\nFloating DIVide (64 bit): assigns f1 to f2 \/ f3<\/td>\n<\/tr>\n
fdiv.s f1, f2, f3<\/td>\n\u6d6e\u52a8 DIVide\uff1a\u5c06 f1 \u5206\u914d\u7ed9 f2 \/ f3<\/td>\nFloating DIVide: assigns f1 to f2 \/ f3<\/td>\n<\/tr>\n
fge.d t1, f2, f3<\/td>\n\u6d6e\u52a8\u5927\u4e8e\u6216\u7b49\u4e8e\uff0864 \u4f4d\uff09\uff1a\u5982\u679c f1 >= f2\uff0c\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 1\uff0c\u5426\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 0<\/td>\nFloating Greater Than or Equal (64 bit): if f1 >= f2, set t1 to 1, else set t1 to 0<\/td>\n<\/tr>\n
fge.s t1, f2, f3<\/td>\n\u6d6e\u52a8\u5927\u4e8e\u6216\u7b49\u4e8e\uff1a\u5982\u679c f1 >= f2\uff0c\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 1\uff0c\u5426\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 0<\/td>\nFloating Greater Than or Equal: if f1 >= f2, set t1 to 1, else set t1 to 0<\/td>\n<\/tr>\n
fgt.d t1, f2, f3<\/td>\n\u6d6e\u52a8\u5927\u4e8e\uff0864 \u4f4d\uff09\uff1a\u5982\u679c f1 > f2\uff0c\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 1\uff0c\u5426\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 0<\/td>\nFloating Greater Than (64 bit): if f1 > f2, set t1 to 1, else set t1 to 0<\/td>\n<\/tr>\n
fgt.s t1, f2, f3<\/td>\n\u6d6e\u52a8\u5927\u4e8e\uff1a\u5982\u679c f1 > f2\uff0c\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 1\uff0c\u5426\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 0<\/td>\nFloating Greater Than: if f1 > f2, set t1 to 1, else set t1 to 0<\/td>\n<\/tr>\n
fld f1,(t2)<\/td>\nLoad Word\uff1a\u5c06f1\u8bbe\u7f6e\u4e3a\u4ece\u6709\u6548\u5185\u5b58\u5b57\u5730\u5740\u5f00\u59cb\u768464\u4f4d\u503c<\/td>\nLoad Word: Set f1 to 64-bit value from effective memory word address<\/td>\n<\/tr>\n
fld f1,-100<\/td>\nLoad Word\uff1a\u5c06f1\u8bbe\u7f6e\u4e3a\u4ece\u6709\u6548\u5185\u5b58\u5b57\u5730\u5740\u5f00\u59cb\u768464\u4f4d\u503c<\/td>\nLoad Word: Set f1 to 64-bit value from effective memory word address<\/td>\n<\/tr>\n
fld f1,10000000,t3<\/td>\nLoad Word\uff1a\u4f7f\u7528 t3 \u4f5c\u4e3a\u4e34\u65f6\u5730\u5740\uff0c\u5c06 f1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u5b57\u5730\u5740\u7684 64 \u4f4d\u503c<\/td>\nLoad Word: Set f1 to 64-bit value from effective memory word address using t3 as a temporary<\/td>\n<\/tr>\n
fld f1,label, t3<\/td>\nLoad Word\uff1a\u4f7f\u7528 t3 \u4f5c\u4e3a\u4e34\u65f6\u5730\u5740\uff0c\u5c06 f1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u5b57\u5730\u5740\u7684 64 \u4f4d\u503c<\/td>\nLoad Word: Set f1 to 64-bit value from effective memory word address using t3 as a temporary<\/td>\n<\/tr>\n
flw f1,%lo(label)(t2)<\/td>\n\u4ece\u5730\u5740\u52a0\u8f7d<\/td>\nLoad from Address<\/td>\n<\/tr>\n
flw f1,(t2)<\/td>\n\u52a0\u8f7d\u5b57\u534f\u5904\u7406\u5668 1\uff1a\u5c06 f1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u5b57\u5730\u5740\u7684 32 \u4f4d\u503c<\/td>\nLoad Word Coprocessor 1 : Set f1 to 32-bit value from effective memory word address<\/td>\n<\/tr>\n
flw f1,-100<\/td>\n\u52a0\u8f7d\u5b57\u534f\u5904\u7406\u5668 1\uff1a\u5c06 f1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u5b57\u5730\u5740\u7684 32 \u4f4d\u503c<\/td>\nLoad Word Coprocessor 1 : Set f1 to 32-bit value from effective memory word address<\/td>\n<\/tr>\n
flw f1,10000000,t3<\/td>\n\u52a0\u8f7d\u5b57\u534f\u5904\u7406\u5668 1\uff1a\u4f7f\u7528 t3 \u4f5c\u4e3a\u4e34\u65f6\u5730\u5740\uff0c\u5c06 f1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u5b57\u5730\u5740\u7684 32 \u4f4d\u503c<\/td>\nLoad Word Coprocessor 1 : Set f1 to 32-bit value from effective memory word address using t3 as a temporary<\/td>\n<\/tr>\n
flw f1,label, t3<\/td>\n\u52a0\u8f7d\u5b57\u534f\u5904\u7406\u5668 1\uff1a\u4f7f\u7528 t3 \u4f5c\u4e3a\u4e34\u65f6\u5730\u5740\uff0c\u5c06 f1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u5b57\u5730\u5740\u7684 32 \u4f4d\u503c<\/td>\nLoad Word Coprocessor 1 : Set f1 to 32-bit value from effective memory word address using t3 as a temporary<\/td>\n<\/tr>\n
flwd f1,%lo(label)(t2)<\/td>\n\u4ece\u5730\u5740\u52a0\u8f7d<\/td>\nLoad from Address<\/td>\n<\/tr>\n
fmadd.d f1, f2, f3, f4<\/td>\n\u878d\u5408\u4e58\u52a0\uff0864 \u4f4d\uff09\uff1a\u5c06 f2*f3+f4 \u5206\u914d\u7ed9 f1<\/td>\nFused Multiply Add (64 bit): Assigns f2*f3+f4 to f1<\/td>\n<\/tr>\n
fmadd.s f1, f2, f3, f4<\/td>\n\u878d\u5408\u4e58\u52a0\uff1a\u5c06 f2*f3+f4 \u5206\u914d\u7ed9 f1<\/td>\nFused Multiply Add: Assigns f2*f3+f4 to f1<\/td>\n<\/tr>\n
fmsub.d f1, f2, f3, f4<\/td>\n\u878d\u5408\u4e58\u6cd5\u51cf\u6cd5\uff0864 \u4f4d\uff09\uff1a\u5c06 f2*f3-f4 \u5206\u914d\u7ed9 f1<\/td>\nFused Multiply Subatract (64 bit): Assigns f2*f3-f4 to f1<\/td>\n<\/tr>\n
fmsub.s f1, f2, f3, f4<\/td>\n\u878d\u5408\u4e58\u5b50\uff1a\u5c06 f2*f3-f4 \u5206\u914d\u7ed9 f1<\/td>\nFused Multiply Subatract: Assigns f2*f3-f4 to f1<\/td>\n<\/tr>\n
fmul.d f1, f2, f3<\/td>\nFloating MULtiply\uff0864 \u4f4d\uff09\uff1a\u5c06 f1 \u5206\u914d\u7ed9 f2 * f3<\/td>\nFloating MULtiply (64 bit): assigns f1 to f2 * f3<\/td>\n<\/tr>\n
fmul.s f1, f2, f3<\/td>\nFloating MULtiply\uff1a\u5c06 f1 \u5206\u914d\u7ed9 f2 * f3<\/td>\nFloating MULtiply: assigns f1 to f2 * f3<\/td>\n<\/tr>\n
fmv.d f1, f2<\/td>\n\u5c06 f2 \u7684\u503c\u79fb\u52a8\u5230 f1\uff0864 \u4f4d\uff09<\/td>\nMove the value of f2 to f1 (64 bit)<\/td>\n<\/tr>\n
fmv.s f1, f2<\/td>\n\u5c06 f2 \u7684\u503c\u79fb\u52a8\u5230 f1<\/td>\nMove the value of f2 to f1<\/td>\n<\/tr>\n
fmv.w.x t1, f1<\/td>\n\u79fb\u52a8\u6d6e\u70b9\u6570\uff08\u65b0\u52a9\u8bb0\u7b26\uff09\uff1a\u4ece\u6574\u6570\u5bc4\u5b58\u5668\u4e2d\u79fb\u52a8\u8868\u793a\u6d6e\u70b9\u6570\u7684\u4f4d<\/td>\nMove float (New mnemonic): move bits representing a float from an integer register<\/td>\n<\/tr>\n
fmv.x.w t1, f1<\/td>\n\u79fb\u52a8\u6d6e\u70b9\u6570\uff08\u65b0\u52a9\u8bb0\u7b26\uff09\uff1a\u5c06\u8868\u793a\u6d6e\u70b9\u6570\u7684\u4f4d\u79fb\u52a8\u5230\u6574\u6570\u5bc4\u5b58\u5668<\/td>\nMove float (New mnemonic): move bits representing a float to an integer register<\/td>\n<\/tr>\n
fneg.d f1, f2<\/td>\n\u5c06 f1 \u8bbe\u7f6e\u4e3a f2 \u7684\u5426\u5b9a\uff0864 \u4f4d\uff09<\/td>\nSet f1 to the negation of f2 (64 bit)<\/td>\n<\/tr>\n
fneg.s f1, f2<\/td>\n\u5c06 f1 \u8bbe\u7f6e\u4e3a f2 \u7684\u5426\u5b9a<\/td>\nSet f1 to the negation of f2<\/td>\n<\/tr>\n
fnmadd.d f1, f2, f3, f4<\/td>\nFused Negate Multiply Add\uff0864 \u4f4d\uff09\uff1a\u5c06 -(f2*f3+f4) \u5206\u914d\u7ed9 f1<\/td>\nFused Negate Multiply Add (64 bit): Assigns -(f2*f3+f4) to f1<\/td>\n<\/tr>\n
fnmadd.s f1, f2, f3, f4<\/td>\nFused Negate Multiply Add\uff1a\u5c06 -(f2*f3+f4) \u5206\u914d\u7ed9 f1<\/td>\nFused Negate Multiply Add: Assigns -(f2*f3+f4) to f1<\/td>\n<\/tr>\n
fnmsub.d f1, f2, f3, f4<\/td>\n\u878d\u5408\u53d6\u53cd\u4e58\u6cd5\u51cf\u6cd5\uff0864 \u4f4d\uff09\uff1a\u5c06 -(f2*f3-f4) \u5206\u914d\u7ed9 f1<\/td>\nFused Negated Multiply Subatract (64 bit): Assigns -(f2*f3-f4) to f1<\/td>\n<\/tr>\n
fnmsub.s f1, f2, f3, f4<\/td>\n\u878d\u5408\u53d6\u53cd\u4e58\u6cd5\u51cf\u6cd5\uff1a\u5c06 -(f2*f3-f4) \u8d4b\u503c\u7ed9 f1<\/td>\nFused Negated Multiply Subatract: Assigns -(f2*f3-f4) to f1<\/td>\n<\/tr>\n
frcsr t1<\/td>\n\u8bfb\u53d6 FP \u63a7\u5236\/\u72b6\u6001\u5bc4\u5b58\u5668<\/td>\nRead FP control\/status register<\/td>\n<\/tr>\n
frflags t1<\/td>\n\u8bfb\u53d6 FP \u5f02\u5e38\u6807\u5fd7<\/td>\nRead FP exception flags<\/td>\n<\/tr>\n
frrm t1<\/td>\n\u8bfb\u53d6 FP \u820d\u5165\u6a21\u5f0f<\/td>\nRead FP rounding mode<\/td>\n<\/tr>\n
frsr t1<\/td>\nfrcsr t1 \u7684\u522b\u540d<\/td>\nAlias for frcsr t1<\/td>\n<\/tr>\n
fscsr t1<\/td>\n\u5199 FP \u63a7\u5236\/\u72b6\u6001\u5bc4\u5b58\u5668<\/td>\nWrite FP control\/status register<\/td>\n<\/tr>\n
fscsr t1, t2<\/td>\n\u4ea4\u6362 FP \u63a7\u5236\/\u72b6\u6001\u5bc4\u5b58\u5668<\/td>\nSwap FP control\/status register<\/td>\n<\/tr>\n
fsd f1,(t2)<\/td>\nStore Word\uff1a\u5c06f1\u4e2d\u768464\u4f4d\u503c\u5b58\u50a8\u5230\u6709\u6548\u5185\u5b58\u5b57\u5730\u5740<\/td>\nStore Word: Store 64-bit value from f1 to effective memory word address<\/td>\n<\/tr>\n
fsd f1,-100<\/td>\nStore Word\uff1a\u5c06f1\u4e2d\u768464\u4f4d\u503c\u5b58\u50a8\u5230\u6709\u6548\u5185\u5b58\u5b57\u5730\u5740<\/td>\nStore Word: Store 64-bit value from f1 to effective memory word address<\/td>\n<\/tr>\n
fsd f1,10000000,t3<\/td>\nStore Word\uff1a\u5c0664\u4f4d\u503c\u4ecef1\u5b58\u50a8\u5230\u6709\u6548\u5185\u5b58\u5b57\u5730\u5740\uff0c\u4f7f\u7528t3\u4f5c\u4e3a\u4e34\u65f6\u5730\u5740<\/td>\nStore Word: Store 64-bit value from f1 to effective memory word address using t3 as a temporary<\/td>\n<\/tr>\n
fsd f1,label, t3<\/td>\nStore Word\uff1a\u5c0664\u4f4d\u503c\u4ecef1\u5b58\u50a8\u5230\u6709\u6548\u5185\u5b58\u5b57\u5730\u5740\uff0c\u4f7f\u7528t3\u4f5c\u4e3a\u4e34\u65f6\u5730\u5740<\/td>\nStore Word: Store 64-bit value from f1 to effective memory word address using t3 as a temporary<\/td>\n<\/tr>\n
fsflags t1<\/td>\n\u5199\u5165 FP \u5f02\u5e38\u6807\u5fd7<\/td>\nWrite FP exception flags<\/td>\n<\/tr>\n
fsflags t1, t2<\/td>\n\u4ea4\u6362 FP \u5f02\u5e38\u6807\u5fd7<\/td>\nSwap FP exception flags<\/td>\n<\/tr>\n
fsflagsi 100<\/td>\n\u7acb\u5373\u5199\u5165 FP \u5f02\u5e38\u6807\u5fd7<\/td>\nWrite FP exception flags, immediate<\/td>\n<\/tr>\n
fsflagsi t1, 100<\/td>\n\u7acb\u5373\u4ea4\u6362 FP \u5f02\u5e38\u6807\u5fd7<\/td>\nSwap FP exception flags, immediate<\/td>\n<\/tr>\n
fsqrt.d f1, f2<\/td>\n\u6d6e\u52a8\u5e73\u65b9\u6839\uff0864 \u4f4d\uff09\uff1a\u5c06 f1 \u5206\u914d\u7ed9 f2 \u7684\u5e73\u65b9\u6839<\/td>\nFloating SQuare RooT (64 bit): Assigns f1 to the square root of f2<\/td>\n<\/tr>\n
fsqrt.s f1, f2<\/td>\n\u6d6e\u52a8\u5e73\u65b9\u6839\uff1a\u5c06 f1 \u5206\u914d\u7ed9 f2 \u7684\u5e73\u65b9\u6839<\/td>\nFloating SQuare RooT: Assigns f1 to the square root of f2<\/td>\n<\/tr>\n
fsrm t1<\/td>\n\u5199\u5165 FP \u820d\u5165\u6a21\u5f0f<\/td>\nWrite FP rounding mode<\/td>\n<\/tr>\n
fsrm t1, t2<\/td>\n\u4ea4\u6362 FP \u820d\u5165\u6a21\u5f0f<\/td>\nSwap FP rounding mode<\/td>\n<\/tr>\n
fsrmi 100<\/td>\n\u5199\u5165 FP \u820d\u5165\u6a21\u5f0f\uff0c\u7acb\u5373\u6570<\/td>\nWrite FP rounding mode, immediate<\/td>\n<\/tr>\n
fsrmi t1, 100<\/td>\n\u4ea4\u6362 FP \u820d\u5165\u6a21\u5f0f\uff0c\u7acb\u5373\u6570<\/td>\nSwap FP rounding mode, immediate<\/td>\n<\/tr>\n
fssr t1<\/td>\nfscsr t1 \u7684\u522b\u540d<\/td>\nAlias for fscsr t1<\/td>\n<\/tr>\n
fssr t1, t2<\/td>\nfscsr t1\u3001t2 \u7684\u522b\u540d<\/td>\nAlias for fscsr t1, t2<\/td>\n<\/tr>\n
fsub.d f1, f2, f3<\/td>\n\u6d6e\u52a8\u51cf\u6cd5\uff0864 \u4f4d\uff09\uff1a\u5c06 f1 \u5206\u914d\u7ed9 f2 - f3<\/td>\nFloating SUBtract (64 bit): assigns f1 to f2 - f3<\/td>\n<\/tr>\n
fsub.s f1, f2, f3<\/td>\n\u6d6e\u52a8\u51cf\u6cd5\uff1a\u5c06 f1 \u5206\u914d\u7ed9 f2 - f3<\/td>\nFloating SUBtract: assigns f1 to f2 - f3<\/td>\n<\/tr>\n
fsw f1,(t2)<\/td>\nStore Word Coprocessor 1 : \u5c06 f1 \u7684 32 \u4f4d\u503c\u5b58\u50a8\u5230\u6709\u6548\u5185\u5b58\u5b57\u5730\u5740<\/td>\nStore Word Coprocessor 1 : Store 32-bit value from f1 to effective memory word address<\/td>\n<\/tr>\n
fsw f1,-100<\/td>\nStore Word Coprocessor 1 : \u5c06 f1 \u7684 32 \u4f4d\u503c\u5b58\u50a8\u5230\u6709\u6548\u5185\u5b58\u5b57\u5730\u5740<\/td>\nStore Word Coprocessor 1 : Store 32-bit value from f1 to effective memory word address<\/td>\n<\/tr>\n
fsw f1,10000000,t3<\/td>\n\u5b58\u50a8\u5b57\u534f\u5904\u7406\u5668 1\uff1a\u5c06 f1 \u7684 32 \u4f4d\u503c\u5b58\u50a8\u5230\u6709\u6548\u5185\u5b58\u5b57\u5730\u5740\uff0c\u4f7f\u7528 t3 \u4f5c\u4e3a\u4e34\u65f6\u5730\u5740<\/td>\nStore Word Coprocessor 1 : Store 32-bit value from f1 to effective memory word address using t3 as a temporary<\/td>\n<\/tr>\n
fsw f1,label, t3<\/td>\n\u5b58\u50a8\u5b57\u534f\u5904\u7406\u5668 1\uff1a\u5c06 f1 \u7684 32 \u4f4d\u503c\u5b58\u50a8\u5230\u6709\u6548\u5185\u5b58\u5b57\u5730\u5740\uff0c\u4f7f\u7528 t3 \u4f5c\u4e3a\u4e34\u65f6\u5730\u5740<\/td>\nStore Word Coprocessor 1 : Store 32-bit value from f1 to effective memory word address using t3 as a temporary<\/td>\n<\/tr>\n
j label<\/td>\n\u8df3\u8f6c\uff1a\u8df3\u8f6c\u5230\u6807\u7b7e\u5904\u7684\u8bed\u53e5<\/td>\nJump : Jump to statement at label<\/td>\n<\/tr>\n
jal label<\/td>\nJump And Link\uff1a\u8df3\u8f6c\u5230\u6807\u53f7\u5904\u7684\u8bed\u53e5\u5e76\u5c06\u8fd4\u56de\u5730\u5740\u8bbe\u7f6e\u4e3ara<\/td>\nJump And Link: Jump to statement at label and set the return address to ra<\/td>\n<\/tr>\n
jalr t0<\/td>\nJump And Link Register\uff1a\u8df3\u8f6c\u5230t0\u4e2d\u7684\u5730\u5740\u5e76\u5c06\u8fd4\u56de\u5730\u5740\u8bbe\u7f6e\u4e3ara<\/td>\nJump And Link Register: Jump to address in t0 and set the return address to ra<\/td>\n<\/tr>\n
jalr t0, -100<\/td>\nJump And Link Register\uff1a\u8df3\u8f6c\u5230t0\u4e2d\u7684\u5730\u5740\u5e76\u5c06\u8fd4\u56de\u5730\u5740\u8bbe\u7f6e\u4e3ara<\/td>\nJump And Link Register: Jump to address in t0 and set the return address to ra<\/td>\n<\/tr>\n
jr t0<\/td>\n\u8df3\u8f6c\u5bc4\u5b58\u5668\uff1a\u8df3\u8f6c\u5230 t0 \u4e2d\u7684\u5730\u5740<\/td>\nJump Register: Jump to address in t0<\/td>\n<\/tr>\n
jr t0, -100<\/td>\n\u8df3\u8f6c\u5bc4\u5b58\u5668\uff1a\u8df3\u8f6c\u5230 t0 \u4e2d\u7684\u5730\u5740<\/td>\nJump Register: Jump to address in t0<\/td>\n<\/tr>\n
la t1,label<\/td>\n\u52a0\u8f7d\u5730\u5740\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\u6807\u7b7e\u7684\u5730\u5740<\/td>\nLoad Address : Set t1 to label's address<\/td>\n<\/tr>\n
lb t1,(t2)<\/td>\n\u52a0\u8f7d\u5b57\u8282\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u5b57\u8282\u5730\u5740\u7684\u7b26\u53f7\u6269\u5c55 8 \u4f4d\u503c<\/td>\nLoad Byte : Set t1 to sign-extended 8-bit value from effective memory byte address<\/td>\n<\/tr>\n
lb t1,-100<\/td>\n\u52a0\u8f7d\u5b57\u8282\uff1a\u5c06 $1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u5b57\u8282\u5730\u5740\u7684\u7b26\u53f7\u6269\u5c55 8 \u4f4d\u503c<\/td>\nLoad Byte : Set $1 to sign-extended 8-bit value from effective memory byte address<\/td>\n<\/tr>\n
lb t1,10000000<\/td>\n\u52a0\u8f7d\u5b57\u8282\uff1a\u5c06 $t1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u5b57\u8282\u5730\u5740\u7684\u7b26\u53f7\u6269\u5c55 8 \u4f4d\u503c<\/td>\nLoad Byte : Set $t1 to sign-extended 8-bit value from effective memory byte address<\/td>\n<\/tr>\n
lb t1,label<\/td>\n\u52a0\u8f7d\u5b57\u8282\uff1a\u5c06 $t1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u5b57\u8282\u5730\u5740\u7684\u7b26\u53f7\u6269\u5c55 8 \u4f4d\u503c<\/td>\nLoad Byte : Set $t1 to sign-extended 8-bit value from effective memory byte address<\/td>\n<\/tr>\n
lbu t1,(t2)<\/td>\n\u52a0\u8f7d\u65e0\u7b26\u53f7\u5b57\u8282\uff1a\u5c06 $t1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u5b57\u8282\u5730\u5740\u7684\u96f6\u6269\u5c55 8 \u4f4d\u503c<\/td>\nLoad Byte Unsigned : Set $t1 to zero-extended 8-bit value from effective memory byte address<\/td>\n<\/tr>\n
lbu t1,-100<\/td>\n\u52a0\u8f7d\u65e0\u7b26\u53f7\u5b57\u8282\uff1a\u5c06 $t1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u5b57\u8282\u5730\u5740\u7684\u96f6\u6269\u5c55 8 \u4f4d\u503c<\/td>\nLoad Byte Unsigned : Set $t1 to zero-extended 8-bit value from effective memory byte address<\/td>\n<\/tr>\n
lbu t1,10000000<\/td>\nLoad Byte Unsigned\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u5b57\u8282\u5730\u5740\u7684\u96f6\u6269\u5c55 8 \u4f4d\u503c<\/td>\nLoad Byte Unsigned : Set t1 to zero-extended 8-bit value from effective memory byte address<\/td>\n<\/tr>\n
lbu t1,label<\/td>\nLoad Byte Unsigned\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u5b57\u8282\u5730\u5740\u7684\u96f6\u6269\u5c55 8 \u4f4d\u503c<\/td>\nLoad Byte Unsigned : Set t1 to zero-extended 8-bit value from effective memory byte address<\/td>\n<\/tr>\n
lh t1,(t2)<\/td>\n\u52a0\u8f7d\u534a\u5b57\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u534a\u5b57\u5730\u5740\u7684\u7b26\u53f7\u6269\u5c55 16 \u4f4d\u503c<\/td>\nLoad Halfword : Set t1 to sign-extended 16-bit value from effective memory halfword address<\/td>\n<\/tr>\n
lh t1,-100<\/td>\n\u52a0\u8f7d\u534a\u5b57\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u534a\u5b57\u5730\u5740\u7684\u7b26\u53f7\u6269\u5c55 16 \u4f4d\u503c<\/td>\nLoad Halfword : Set t1 to sign-extended 16-bit value from effective memory halfword address<\/td>\n<\/tr>\n
lh t1,10000000<\/td>\n\u52a0\u8f7d\u534a\u5b57\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u534a\u5b57\u5730\u5740\u7684\u7b26\u53f7\u6269\u5c55 16 \u4f4d\u503c<\/td>\nLoad Halfword : Set t1 to sign-extended 16-bit value from effective memory halfword address<\/td>\n<\/tr>\n
lh t1,label<\/td>\n\u52a0\u8f7d\u534a\u5b57\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u534a\u5b57\u5730\u5740\u7684\u7b26\u53f7\u6269\u5c55 16 \u4f4d\u503c<\/td>\nLoad Halfword : Set t1 to sign-extended 16-bit value from effective memory halfword address<\/td>\n<\/tr>\n
lhu t1,(t2)<\/td>\n\u52a0\u8f7d\u65e0\u7b26\u53f7\u534a\u5b57\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u534a\u5b57\u5730\u5740\u7684\u96f6\u6269\u5c55 16 \u4f4d\u503c<\/td>\nLoad Halfword Unsigned : Set t1 to zero-extended 16-bit value from effective memory halfword address<\/td>\n<\/tr>\n
lhu t1,-100<\/td>\n\u52a0\u8f7d\u65e0\u7b26\u53f7\u534a\u5b57\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u534a\u5b57\u5730\u5740\u7684\u96f6\u6269\u5c55 16 \u4f4d\u503c<\/td>\nLoad Halfword Unsigned : Set t1 to zero-extended 16-bit value from effective memory halfword address<\/td>\n<\/tr>\n
lhu t1,10000000<\/td>\n\u52a0\u8f7d\u65e0\u7b26\u53f7\u534a\u5b57\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u534a\u5b57\u5730\u5740\u7684\u96f6\u6269\u5c55 16 \u4f4d\u503c<\/td>\nLoad Halfword Unsigned : Set t1 to zero-extended 16-bit value from effective memory halfword address<\/td>\n<\/tr>\n
lhu t1,label<\/td>\n\u52a0\u8f7d\u65e0\u7b26\u53f7\u534a\u5b57\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u534a\u5b57\u5730\u5740\u7684\u96f6\u6269\u5c55 16 \u4f4d\u503c<\/td>\nLoad Halfword Unsigned : Set t1 to zero-extended 16-bit value from effective memory halfword address<\/td>\n<\/tr>\n
li t1,-100<\/td>\n\u7acb\u5373\u52a0\u8f7d\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a 12 \u4f4d\u7acb\u5373\u6570\uff08\u7b26\u53f7\u6269\u5c55\uff09<\/td>\nLoad Immediate : Set t1 to 12-bit immediate (sign-extended)<\/td>\n<\/tr>\n
li t1,10000000<\/td>\n\u7acb\u5373\u52a0\u8f7d\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a 32 \u4f4d\u7acb\u5373\u6570<\/td>\nLoad Immediate : Set t1 to 32-bit immediate<\/td>\n<\/tr>\n
lui t1,%hi(label)<\/td>\nLoad Upper Address : \u5c06 t1 \u8bbe\u7f6e\u4e3a\u6807\u7b7e\u7684\u9ad8 20 \u4f4d\u5730\u5740<\/td>\nLoad Upper Address : Set t1 to upper 20-bit label's address<\/td>\n<\/tr>\n
lw t1,%lo(label)(t2)<\/td>\n\u4ece\u5730\u5740\u52a0\u8f7d<\/td>\nLoad from Address<\/td>\n<\/tr>\n
lw t1,(t2)<\/td>\n\u52a0\u8f7d\u5b57\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u5b57\u5730\u5740\u7684\u5185\u5bb9<\/td>\nLoad Word : Set t1 to contents of effective memory word address<\/td>\n<\/tr>\n
lw t1,-100<\/td>\n\u52a0\u8f7d\u5b57\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u5b57\u5730\u5740\u7684\u5185\u5bb9<\/td>\nLoad Word : Set t1 to contents of effective memory word address<\/td>\n<\/tr>\n
lw t1,10000000<\/td>\n\u52a0\u8f7d\u5b57\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\u6709\u6548\u5185\u5b58\u5b57\u5730\u5740\u7684\u5185\u5bb9<\/td>\nLoad Word : Set t1 to contents of effective memory word address<\/td>\n<\/tr>\n
lw t1,label<\/td>\n\u52a0\u8f7d\u5b57\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a\u6807\u7b7e\u5730\u5740\u5904\u5185\u5b58\u5b57\u7684\u5185\u5bb9<\/td>\nLoad Word : Set t1 to contents of memory word at label's address<\/td>\n<\/tr>\n
mv t1,t2<\/td>\nMoVe\uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a t2 \u7684\u5185\u5bb9<\/td>\nMoVe : Set t1 to contents of t2<\/td>\n<\/tr>\n
neg t1,t2<\/td>\nNEGate \uff1a\u5c06 t1 \u8bbe\u7f6e\u4e3a t2 \u7684\u5426\u5b9a<\/td>\nNEGate : Set t1 to negation of t2<\/td>\n<\/tr>\n
nop<\/td>\n\u65e0\u64cd\u4f5c<\/td>\nNO OPeration<\/td>\n<\/tr>\n
not t1,t2<\/td>\n\u6309\u4f4d\u975e\uff08\u4f4d\u53cd\u8f6c\uff09<\/td>\nBitwise NOT (bit inversion)<\/td>\n<\/tr>\n
rdcycle t1<\/td>\n\u4ece\u5faa\u73af\u4e2d\u8bfb\u53d6<\/td>\nRead from cycle<\/td>\n<\/tr>\n
rdcycleh t1<\/td>\n\u4ece cycleh \u8bfb\u53d6<\/td>\nRead from cycleh<\/td>\n<\/tr>\n
rdinstret t1<\/td>\n\u4eceinstret\u8bfb\u53d6<\/td>\nRead from instret<\/td>\n<\/tr>\n
rdinstreth t1<\/td>\n\u4ece instreth \u8bfb\u53d6<\/td>\nRead from instreth<\/td>\n<\/tr>\n
rdtime t1<\/td>\n\u4ece\u65f6\u95f4\u8bfb<\/td>\nRead from time<\/td>\n<\/tr>\n
rdtimeh t1<\/td>\n\u4ece\u65f6\u95f4\u8bfb\u53d6<\/td>\nRead from timeh<\/td>\n<\/tr>\n
ret<\/td>\n\u8fd4\u56de\uff1a\u4ece\u5b50\u7a0b\u5e8f\u8fd4\u56de<\/td>\nReturn: return from a subroutine<\/td>\n<\/tr>\n
sb t1,(t2)<\/td>\nStore Byte : \u5c06t1\u7684\u4f4e8\u4f4d\u5b58\u5165\u6709\u6548\u5185\u5b58\u5b57\u8282\u5730\u5740<\/td>\nStore Byte : Store the low-order 8 bits of t1 into the effective memory byte address<\/td>\n<\/tr>\n
sb t1,-100<\/td>\nStore Byte : \u5c06$t1\u7684\u4f4e8\u4f4d\u5b58\u5165\u6709\u6548\u5185\u5b58\u5b57\u8282\u5730\u5740<\/td>\nStore Byte : Store the low-order 8 bits of $t1 into the effective memory byte address<\/td>\n<\/tr>\n
sb t1,10000000,t2<\/td>\nStore Byte : \u5c06$t1\u7684\u4f4e8\u4f4d\u5b58\u5165\u6709\u6548\u5185\u5b58\u5b57\u8282\u5730\u5740<\/td>\nStore Byte : Store the low-order 8 bits of $t1 into the effective memory byte address<\/td>\n<\/tr>\n
sb t1,label,t2<\/td>\nStore Byte : \u5c06$t1\u7684\u4f4e8\u4f4d\u5b58\u5165\u6709\u6548\u5185\u5b58\u5b57\u8282\u5730\u5740<\/td>\nStore Byte : Store the low-order 8 bits of $t1 into the effective memory byte address<\/td>\n<\/tr>\n
seqz t1,t2<\/td>\n\u5c06 EQual \u8bbe\u7f6e\u4e3a\u96f6\uff1a\u5982\u679c t2 == 0\uff0c\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 1\uff0c\u5426\u5219\u4e3a 0<\/td>\nSet EQual to Zero : if t2 == 0 then set t1 to 1 else 0<\/td>\n<\/tr>\n
sgt t1,t2,t3<\/td>\n\u8bbe\u7f6e\u5927\u4e8e\uff1a\u5982\u679c t2 \u5927\u4e8e t3\uff0c\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 1\uff0c\u5426\u5219\u4e3a 0<\/td>\nSet Greater Than : if t2 greater than t3 then set t1 to 1 else 0<\/td>\n<\/tr>\n
sgtu t1,t2,t3<\/td>\n\u8bbe\u7f6e\u5927\u4e8e\u65e0\u7b26\u53f7\uff1a\u5982\u679c t2 \u5927\u4e8e t3\uff08\u65e0\u7b26\u53f7\u6bd4\u8f83\uff09\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 1\uff0c\u5426\u5219\u4e3a 0<\/td>\nSet Greater Than Unsigned : if t2 greater than t3 (unsigned compare) then set t1 to 1 else 0<\/td>\n<\/tr>\n
sgtz t1,t2<\/td>\n\u8bbe\u7f6e\u5927\u4e8e\u96f6\uff1a\u5982\u679c t2 > 0\uff0c\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 1\uff0c\u5426\u5219\u4e3a 0<\/td>\nSet Greater Than Zero : if t2 > 0 then set t1 to 1 else 0<\/td>\n<\/tr>\n
sh t1,(t2)<\/td>\nStore Halfword : \u5c06$1\u7684\u4f4e16\u4f4d\u5b58\u5165\u6709\u6548\u5185\u5b58\u534a\u5b57\u5730\u5740<\/td>\nStore Halfword : Store the low-order 16 bits of $1 into the effective memory halfword address<\/td>\n<\/tr>\n
sh t1,-100<\/td>\nStore Halfword : \u5c06$t1\u7684\u4f4e16\u4f4d\u5b58\u5165\u6709\u6548\u5185\u5b58\u534a\u5b57\u5730\u5740<\/td>\nStore Halfword : Store the low-order 16 bits of $t1 into the effective memory halfword address<\/td>\n<\/tr>\n
sh t1,10000000,t2<\/td>\nStore Halfword : \u5c06t1\u7684\u4f4e16\u4f4d\u4ee5t2\u4e3a\u4e34\u65f6\u5b58\u50a8\u5230\u6709\u6548\u5185\u5b58\u534a\u5b57\u5730\u5740<\/td>\nStore Halfword : Store the low-order 16 bits of t1 into the effective memory halfword address using t2 as a temporary<\/td>\n<\/tr>\n
sh t1,label,t2<\/td>\nStore Halfword : \u5c06t1\u7684\u4f4e16\u4f4d\u4ee5t2\u4e3a\u4e34\u65f6\u5b58\u50a8\u5230\u6709\u6548\u5185\u5b58\u534a\u5b57\u5730\u5740<\/td>\nStore Halfword : Store the low-order 16 bits of t1 into the effective memory halfword address using t2 as a temporary<\/td>\n<\/tr>\n
sltz t1,t2<\/td>\n\u8bbe\u7f6e\u5c0f\u4e8e\u96f6\uff1a\u5982\u679c t2 < 0\uff0c\u5219\u5c06 t1 \u8bbe\u7f6e\u4e3a 1\uff0c\u5426\u5219\u4e3a 0<\/td>\nSet Less Than Zero : if t2 < 0 then set t1 to 1 else 0<\/td>\n<\/tr>\n
snez t1,t2<\/td>\n\u8bbe\u7f6e\u4e0d\u7b49\u4e8e\u96f6\uff1aif t2 != 0 then set t1 to 1 else 0<\/td>\nSet Not Equal to Zero : if t2 != 0 then set t1 to 1 else 0<\/td>\n<\/tr>\n
sw t1,(t2)<\/td>\nStore Word : \u5c06 t1 \u7684\u5185\u5bb9\u5b58\u5165\u6709\u6548\u5185\u5b58\u5b57\u5730\u5740<\/td>\nStore Word : Store t1 contents into effective memory word address<\/td>\n<\/tr>\n
sw t1,-100<\/td>\nStore Word : \u5c06$t1\u5185\u5bb9\u5b58\u5165\u6709\u6548\u5185\u5b58\u5b57\u5730\u5740<\/td>\nStore Word : Store $t1 contents into effective memory word address<\/td>\n<\/tr>\n
sw t1,10000000,t2<\/td>\nStore Word\uff1a\u5c06$t1\u7684\u5185\u5bb9\u5b58\u50a8\u5230\u6709\u6548\u7684\u5185\u5b58\u5b57\u5730\u5740\u4e2d\uff0c\u4f7f\u7528t2\u4f5c\u4e3a\u4e34\u65f6\u5730\u5740<\/td>\nStore Word : Store $t1 contents into effective memory word address using t2 as a temporary<\/td>\n<\/tr>\n
sw t1,label,t2<\/td>\nStore Word\uff1a\u5c06$t1 \u7684\u5185\u5bb9\u5b58\u50a8\u5230\u6807\u7b7e\u5730\u5740\u5904\u7684\u5185\u5b58\u5b57\u4e2d\uff0c\u4f7f\u7528t2 \u4f5c\u4e3a\u4e34\u65f6\u5730\u5740<\/td>\nStore Word : Store $t1 contents into memory word at label's address using t2 as a temporary<\/td>\n<\/tr>\n
tail label<\/td>\nTAIL call\uff1a\u5c3e\u8c03\u7528\uff08call without saved return address\uff09a far-away subroutine<\/td>\nTAIL call: tail call (call without saving return address)a far-away subroutine<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

Supported Instructions (\u652f\u6301\u7684\u6307\u4ee4) Example Usage \u4e2d\u6587\u63cf\u8ff0 […]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[12],"tags":[72],"class_list":["post-1257","post","type-post","status-publish","format-standard","hentry","category-learn","tag-riscv"],"_links":{"self":[{"href":"https:\/\/lyvba.com\/index.php\/wp-json\/wp\/v2\/posts\/1257","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/lyvba.com\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/lyvba.com\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/lyvba.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/lyvba.com\/index.php\/wp-json\/wp\/v2\/comments?post=1257"}],"version-history":[{"count":0,"href":"https:\/\/lyvba.com\/index.php\/wp-json\/wp\/v2\/posts\/1257\/revisions"}],"wp:attachment":[{"href":"https:\/\/lyvba.com\/index.php\/wp-json\/wp\/v2\/media?parent=1257"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/lyvba.com\/index.php\/wp-json\/wp\/v2\/categories?post=1257"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/lyvba.com\/index.php\/wp-json\/wp\/v2\/tags?post=1257"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}